Conventional methods of polishing both sides of a semiconductor wafer include the use of a polishing pad with a supply of a polishing agent as stock removal polishing (DSP step), and a final polishing only of the front side (“component side”) using a softer polishing pad as so-called haze-free polishing (CMP step, “finishing”), but also include new so-called “fixed abrasive polishing” (FAP) technologies, in which the semiconductor wafer is polished on a polishing pad which contains an abrasive material bonded in the polishing pad (“fixed-abrasive pad”). A polishing step in which such an FAP polishing pad is used is referred to hereinafter for short as FAP step.
WO 99/55491 A1 describes a two-stage polishing method, comprising a first FAP polishing step and a subsequent second CMP polishing step. In the case of CMP, the polishing pad contains no bonded abrasive material. In this case, as in the case of a DSP step, abrasive material is introduced in the form of a slurry between the semiconductor wafer and the polishing pad. Such a two-stage polishing method is used in particular to eliminate scratches left by the FAP step on the polished surface of the substrate.
EP 1 717 001 A1 is one example of the fact that FAP steps are also used when polishing semiconductor wafers which have not yet had any component structures formed on their surface. During the polishing of such semiconductor wafers, it is primarily important to produce at least one lateral surface which is particularly planar and which has a minimal microroughness and nanotopography.
US 2002/00609967 A1 relates to CMP methods for leveling topographic surfaces during the production of electronic components. The primary endeavor is to alleviate the disadvantage of comparatively low removal rates when using FAP polishing pads. A sequence of polishing steps is proposed wherein polishing is effected firstly using an FAP pad in conjunction with a polishing agent slurry and subsequently using an FAP pad in conjunction with a polishing agent solution. In this case, the order of the steps is chosen in a targeted manner in order to increase the removal rate. The polishing of wafers composed of material having a homogeneous composition, e.g. silicon wafers, is not described therein.
WO 03/074228 A1, too, describes a method for leveling topographic surfaces during the production of electronic components. In this case, the central point of the description is the endpoint recognition in CMP methods. As is known, endpoint recognition involves ending the polishing and hence the material removal in a timely fashion before regions are removed which are specifically not intended to be polished. A two-stage method for polishing a copper layer is proposed for this purpose. In the first step, polishing is effected using an FAP polishing pad, wherein the polishing agent optionally does or does not contain free abrasive particles. In the second polishing step of this method, in which polishing is likewise effected using an FAP pad, the use of a polishing agent with free abrasive particles is, in contrast, essential.
DE 102 007 035 266 A1 describes a method for polishing a substrate composed of semiconductor material, comprising two polishing steps of the FAP type, which differ in that, in one polishing step, a polishing agent slurry containing non-bonded abrasive material as a solid is introduced between the substrate and the polishing pad, while in the second polishing step the polishing agent slurry is replaced by a polishing agent solution that is free of solids.
The conventional polishing methods, in particular the DSP polishing, lead to an unfavorable edge symmetry, in particular to a so-called “edge roll-off”, that is to say to an edge decrease relative to the thickness of the semiconductor wafer.
In principle, the semiconductor wafers are pressed with the aid of a polishing head with their lateral surface to be polished against the polishing pad lying on a polishing plate.
A polishing head also includes a retainer ring, which encloses the substrate laterally and prevents it from sliding off the polishing head during the polishing. Therefore, in order to prevent the transverse forces which occur during the polishing from pushing the wafer from the polishing head, the wafers are held in position by such retainer rings. These devices are described in various patents (U.S. Pat. No. 6,293,850B1; U.S. Pat. No. 6,033,292; EP 1029633A1; U.S. Pat. No. 5,944,590).
The retainer rings are pressed more or less firmly onto the polishing pad.
In modern polishing heads, that lateral surface of the semiconductor wafer which is remote from the polishing pad bears on an elastic membrane which transmits the polishing pressure exerted. The membrane is part of a chamber system, subdivided if appropriate, which can form a gas or liquid cushion (membrane carrier, zone carrier).
The pressure chambers are preferably arranged concentrically or in segmented fashion, and a specific pressure can be applied to them separately from one another. The polishing pressure is finally transmitted to the rear side of a support plate via elastic bearing surfaces of the pressure chambers to which pressure is applied. This applies for example to the multi-plate polishing machine AMAT Reflection from Applied Materials, Inc., which comprises a 5-zone membrane carrier with a differently adjustable pressure profile.
In the case of DSP and CMP, the substrate is polished with supply of a polishing agent between the substrate and the polishing pad and with rotation of the polishing head and the polishing plate.
The German application—not previously published—bearing the file reference 102008053610.5 describes a method for the double-side polishing of a semiconductor wafer, comprising the following steps in the stated order:
a) polishing of a rear side of the semiconductor wafer on a polishing pad which contains an abrasive material bonded in the polishing pad, wherein a polishing agent solution that is free of solids is introduced between the rear side of the semiconductor wafer and the polishing pad during the polishing step;
b) stock removal polishing of the front side of the semiconductor wafer on a polishing pad which contains an abrasive material bonded in the polishing pad, wherein a polishing agent solution that is free of solids is introduced between the front side of the semiconductor wafer and the polishing pad during the polishing step;
c) removal of the microroughness from the front side of the semiconductor wafer by polishing of the front side of the semiconductor wafer on a polishing pad, wherein a polishing agent slurry containing abrasive materials is introduced between the front side of the semiconductor wafer and the polishing pad during the polishing step;
d) final polishing of the front side of the semiconductor wafer by polishing of the front side of the semiconductor wafer on a polishing pad which contains no abrasive material bonded in the polishing pad, wherein a polishing agent slurry containing abrasive materials is introduced between the front side of the semiconductor wafer and the polishing pad during the polishing step.
Steps a) and b) of this method are FAP polishing steps. Step c) can also be carried out in the form of an FAP polishing step, that is to say using a polishing pad comprising fixedly bonded abrasives. Step d) is a typical CMP polishing step.
This method makes it possible to improve the nanotopography of the semiconductor wafer and the edge geometry thereof The DSP step provided in the prior art can be obviated.
On searching for a further improvement in the edge geometry of the semiconductor wafers polished according to this method, the inventors have recognized that, particularly in the case of FAP polishing steps using comparatively hard and stiff FAP polishing pads, the polishing machines and wafer holding systems usually used are in part disadvantageous. This is due to the fact that the hard FAP polishing pads scarcely “yield”, i.e. react only inadequately to pressure from outside (pressure in AMAT 5-zone carrier, retainer ring contact pressure).